"Materials and Device Aspects of III-V 3D Transistors"
Peide (Peter) Ye, School of Electrical and Computer Engineering, Purdue University
Recently, III-V MOSFETs with high drain currents (Ids>1mA/µm) and high transconductances (gm>1mS/µm) have been achieved at sub-micron channel lengths (Lch), thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. The scaling of planar devices stops at around 150nm Lch. The dramatic increase in DIBL beyond 150nm indicates severe impact from 2D electrostatics. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V 3D transistors developed very recently [1-3].
1. Y. Q. Wu et al. IEDM Tech. Dig. 331 (2009).
2. M. Radosavljevic et al., IEDM Tech. Dig. 126 (2010).
Peide (Peter) Ye received the B.S. degree in electrical engineering from Fudan University, Shanghai, China, in 1988 and Ph.D. in solid state physics from Max-Planck-Institute of Solid State Research, Stuttgart, Germany, in 1996. From 1996 to 2000, he was research fellow at NTT Basic Research Laboratories and NHMFL/Princeton University. He joined Bell Laboratories, Murray Hill, NJ and then Agere Systems in 2001 as a Member of Technical Staff and becomes a Senior Member of Technical Staff in 2003. He joined Purdue University in 2005 and is currently professor of electrical and computer engineering. His research activities include semiconductor physics and devices, nano-structures and nano-fabrications, quantum and spin transport, atomic layer deposition, III-V MOSFETs, and recently grapheme based nanoelectronics.