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Mon., April. 2, 2012
10:45 a.m., NSERL 3.204








"Performance and Reliability Investigation of Double-gate FinFETs"
Dr. Chadwin Young, SEMATECH

In order to continue technology scaling to meet future performance needs, multi-gate field effect transistors (MugFETs), are currently under investigation. MugFETs can be fabricated on silicon-on-insulator (SOI), and they are especially attractive because their three-dimensional structure enables excellent immunity to short channel effects, without significant changes to conventional CMOS fabri-cation techniques. One MugFET design of interest is known as the FinFET, where a hard mask is placed on the top surface of a fin structure to decouple it from the sidewall device operation (fig. 1). FinFETs can be fabricated with either the (110) sidewall surface or (100) sidewall where the crystal orientation of the fin sidewalls can have an impact on mobility and thereby provide a mobility boost based on orientation [1-4]. Moreover, the implications of sidewall surface orientation on reliability issues such as hot carriers [5,6] and bias temperature instability [7,8] also need to be addressed. The surface orientation or fin structure may be more susceptible to degradation during stress. Possi-ble causes include: Si interface bonds available for bond breakage [9] in the (110) plane, or struc-tural properties that impact reliability differently than planar devices. In this work, we evaluate the dependence of FinFET sidewall orientation on performance (i.e., mobility and Ion/Ioff) and reliability, where hot carrier injection and BTI are evaluated.

Chadwin D. Young received his B.S. degree in Electrical Engineering from the Univ. of Texas at Austin in 1996 and his M.S. and Ph.D. in EE from the North Carolina State University in 1998 and 2004, respec-tively. In 2001, he joined SEMATECH where he completed his disserta-tion research on high-k gate stacks and continues this research at SE-MATECH as a Senior Member of the Technical Staff working on electri-cal characterization and reliability methodologies for the evaluation of high-k gate stacks on current and future device architectures. He has authored or co-authored 185+ journal and conference papers. He has served: on the management or technical progam committees of IIRW, IRPS, SISC, IEDM, WoDiM; as Guest Editor for IEEE Transactions on Device and Materials Reliability; and as a peer reviewer. He is cur-rently a Senior Member of IEEE.